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Topic Summary - Displaying 1 posts. Click here to show all
Posted by: jaap Posted on: Oct 14th, 2019, 9:47am
Yes, as far as I understand it, the size of a page is always 256 bytes because they simply decoupled the two counter chips in the pack, and the lower counter (plus one input pin) provided the low 8 bits of the pack address. This also allows all the pack access routines to simply use the high byte of the address as the page number.
The segment size is always 16K because that is what the Intel 128K EPROM chips used.
I don't know of any packs that use something different. One kind of exception is the Thesaurus, which does have a page size of 256 but uses a different control mechanism for it on the pins. They put boot code in the first 256 byte page, which when executed then loaded/accessed the rest.
While it is theoretically possible to have a different page/segment size, the Psion would need boot code to replace the pack access routines, similar what the Thesaurus pack does.

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