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POISN
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Pack Geometry
« on: Oct 12th, 2019, 8:17pm »
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I'm thinking about having a go at creating large capacity RAMPaks or Flashpaks. However, I don't understand how the Organiser determines a pack's geometry. By that I mean how many bytes there are per page and how many pages per segment.
 
According to the technical reference manual, these can vary. A 32K RAMPak, if paged, has a page counter that wraps around at 128, but a 128K Datapak has a page counter that wraps around at 64. Perhaps the pack geometry is worked out during sizing, but the pack header only indicates whether the pack is paged and pack size.
 
If a pack is paged and segmented, are there always 256 bytes per page and 64 pages per segment? If not, how does the Organiser know?
thesourcerer
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Re: Pack Geometry
« Reply #1 on: Oct 13th, 2019, 12:33am »
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Olivier Gossuin already produces 512k Flash datapacks and 256k Rampacks. I have a few 512k Rampacks. (I also supply Olivier’s packs).
What sort of sizes were you thinking of?
jaap
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Re: Pack Geometry
« Reply #2 on: Oct 14th, 2019, 9:47am »
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Yes, as far as I understand it, the size of a page is always 256 bytes because they simply decoupled the two counter chips in the pack, and the lower counter (plus one input pin) provided the low 8 bits of the pack address. This also allows all the pack access routines to simply use the high byte of the address as the page number.
The segment size is always 16K because that is what the Intel 128K EPROM chips used.
 
I don't know of any packs that use something different. One kind of exception is the Thesaurus, which does have a page size of 256 but uses a different control mechanism for it on the pins. They put boot code in the first 256 byte page, which when executed then loaded/accessed the rest.
While it is theoretically possible to have a different page/segment size, the Psion would need boot code to replace the pack access routines, similar what the Thesaurus pack does.
« Last Edit: Oct 14th, 2019, 9:48am by jaap »

Jaap Scherphuis
https://www.jaapsch.net/psion/
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