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Posted by: starhawk
Posted on: Jul 13th, 2018, 9:26pm
The problem is that the mainboard layout is CRAZY. I didn't run out of time -- I ran out of patience. A trace will go through three vias, hopping back and forth between sides each time, in the space of an inch-and-a-half -- or less! Whoever laid out the dang thing was either Circuit Merlin, absolutely bats***, both, or a rather gifted Italian chef, because the layout resembles nothing so much as a plate of electronic spaghetti.
I tried to use a straight pin (the vias are juuuust big enough to poke one through) to keep track of what went where how, but even that wasn't enough to keep me straight. So I said eff it.
What I need to do, really, is heatgun all the chips off, and scan both sides of the mainboard. then bring them into an image editor (something like Photoshop), mirror one so they're facing the same way, overlay them, and reduce the opacity of one -- that way all the vias line up and the traces connect and I can effectively see both sides of the board at once. However, I've not had sufficient motivation to do that (I have a form of autism, and that's one of the effects).
Further, while there are indeed technically no ASICs per se, there is a PAL -- programmable array logic, an early precursor to the FPGA -- that someone's going to have to reverse engineer or get the programming for, if we want the complete picture.